This disclosed subject matter pertains to automated manufacturing environments, such as semiconductor manufacturing, and, more particularly, to a method and apparatus for routing wafer pods to allow parallel processing.
Growing technological requirements and the worldwide acceptance of sophisticated electronic devices have created an unprecedented demand for large-scale, complex, integrated circuits. Competition in the semiconductor industry requires that products be designed, manufactured, and marketed in the most efficient manner possible. This requires improvements in fabrication technology to keep pace with the rapid improvements in the electronics industry. Meeting these demands spawns many technological advances in materials and processing equipment and significantly increases the number of integrated circuit designs. These improvements also require effective utilization of computing resources and other highly sophisticated equipment to aid, not only design and fabrication, but also the scheduling, control, and automation of the manufacturing process.
Turning first to fabrication, integrated circuits, or microchips, are manufactured from modern semiconductor devices containing numerous structures or features, typically the size of a few micrometers or less. The features are placed in localized areas of a semiconducting substrate, and are either conductive, non-conductive, or semi-conductive (i.e., rendered conductive in defined areas with dopants). The fabrication process generally involves processing a number of wafers through a series of fabrication tools. Each fabrication tool performs one or more of four basic operations discussed more fully below. The four basic operations are performed in accordance with an overall process to finally produce the finished semiconductor devices.
Integrated circuits are manufactured from wafers of a semiconducting substrate material. Layers of materials are added, removed, and/or treated during fabrication to create the integrated, electrical circuits that make up the device. The fabrication essentially comprises the following four basic operations:                layering, or adding thin layers of various materials to a wafer from which a semiconductor is produced;        patterning, or removing selected portions of added layers;        doping, or placing specific amounts of dopants in selected portions of the wafer through openings in the added layers; and        heat treating, or heating and cooling the materials to produce desired effects in the processed wafer.        
Although there are only four basic operations, they can be combined in hundreds of different ways, depending upon the particular fabrication process.
To facilitate processing of wafers through a process flow, wafers are typically grouped into lots. Each lot is typically housed in a common wafer pod wafer, commonly referred to as front opening unified pod (FOUP). FOUPs or pods are transported to various process and metrology tools throughout the fabrication facility to allow the required processes to be completed to fabricate integrated circuit devices on the wafers.
Modern wafer fabrication facilities employ automated material movement systems to satisfy ergonomic concerns and to maintain a high level of automation. An interbay/intrabay vehicle automated material handling system (AMHS) may be employed to automate the transfer of wafers to the tools required in the process flow. One factor contributing to the efficiency of the material handling system is the delivery time between tools. Delivery time may vary depending on the distance between tools, the congestion of the tools, and the distance an idle material handling vehicle needs to travel to pick up a waiting wafer pod.
A semiconductor foundry, commonly referred to as a fab, attempts to streamline its manufacturing operations and measures success using specific attributes such as: quality of delivery (cycle time, just in time), quality of the process and product (yield, product performance), quantity (throughput), and cost (wafer/die cost). While tuning the foundry for just one of these factors is rather simple, a more holistic approach needs to provide the right balance by optimizing the operational scenarios, lot and batch sizes, equipment qualification scenarios, etc.
Considering state of the art facilities, regular production runs in 300 mm fabs facilitate lots of 25 wafers in a wafer pod. An automated material handling system in conjunction with a Manufacturing Execution System (MES) manages the transportation and tracking of pods. Fabs with up to 150K wafer starts per month can have a Work In Process (WIP) in excess of half a million wafers. The corresponding inventory requires huge stocker capacities. The inventory represents a considerable amount of bound capacity with the associated risk and also the required stocker capacity mandates a significant investment in automation equipment and floor space.
A reduction of cycle time will reduce inventory, at the same time reducing the capital risk and relaxing the requirements for stockers. A short cycle time also helps identifying yield and design issues quicker, thus enabling the improvement of the quality of process and products. It is important to note that, while cycle time reduction seems to provide means to improve many fab performance attributes, a reduction of cycle time should usually not be performed at the expense of throughput.
Looking further into the topic of cycle time reveals that during manufacturing, wafers in a pod spend hours waiting for the next equipment to become available for processing. Unfortunately this waiting time cannot easily be eliminated because a certain amount of WIP has to be present at every operation to enable efficient use of the capital invested in the equipment. But even after arrival at the equipment, wafers in the pods spend considerable time sitting idle on load ports (LP) waiting for the previous lot to finish, waiting for the first wafers of their own lots to finish processing or waiting for the remaining wafers in their lot to finish processing.
In addition to production routes, the AMHS and MES manage the flow for non-product wafers. For instance on a typical monitoring route, test wafers (TWs) go through a series of pre-measurement steps, get processed on a tool (either for tool qualification purpose or for process monitoring) and then finally go through a series of post measurement steps. For better (and simpler) management of reserving and dispatching test wafers, the tendency has been to consolidate the test wafers into logical units called test wafer kits and then to physically consolidate them in single pod if the source wafers are scattered in multiple pods at the time the kit is specified.
The conventional qualification process requires the usage of a wafer sorter for assembling and disassembling the wafers in a single pod, and sequential processing of the test wafers in the metrology chains. The sorting and sequential processing constraints result in an increase in time required to complete the processing of the kit to accomplish the qualification or process monitoring goal.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.